In general, a time amplifier is used to increase the resolution of a time-to-digital converter (TDC) or a phase-locked loop (PLL). Basically, a time amplifier employs an SR latch (disclosed in Korean Patent Publication No. 10-2014-0125950 (published on Oct. 30, 2014)) and a gain amplifier to amplify a time difference (input value) between two input signals using metastability of a transistor.
For example, a conventional time amplifier generates two output pulses for a regeneration time after amplifying a difference between two input times of two input signals by a gain of a gain amplifier. The regeneration time means a time until two input pulses are output since they were input. If the regeneration time increases, the gain of the gain amplifier also increases. However, a capacitor included in the time amplifier has suffered from the disadvantage that power consumption finally increases as the amount and voltage of current generated during charging/discharging increase.
Additionally, to reduce the above-mentioned power consumption, the conventional time amplifier may reduce the regeneration time by decreasing a high gain after giving an output of the gain. Unfortunately, the conventional time amplifier has suffered from the disadvantages that the gain is limited to a minimum gain and power consumption increases due to a voltage charged to a capacitor.